DS3105LN+【PDF 43/124 页】IC TIMING LINE CARD 64-LQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录1994

39页 40页 41页 42页 [43页]44页 45页 46页 47页

DS3105

7.7

DPLL Architecture and Configuration

Both the T0 DPLL and T4 DPLL are digital PLLs. The T0 DPLL has separate analog PLLs (APLLs) as output

stages as well as some outputs that are not cleaned up by an APLL. This architecture combines the benefits of

both PLL types. See Figure 7-1.

Figure 7-1. DPLL Block Diagram

T0 DPLL

T4 DPLL

Locking

Frequency

PFD and

Loop Filter

Foward

DFS

Feedback

DFS

DIG12

DFS

T0 selected

reference

OC3, OC6

Foward

DFS

Feedback

DFS

PFD and

Loop Filter

Locking

Frequency

T4 selected

reference

T0CR1:T0FREQ[2:0]

OCRm:OFREQn[3:0]

OCR5:AOFn

T0CR1:T4MT0

T4CR1:T4FREQ[3:0]

T0CR1:T0FT4[2:0]

APLL

Output

Dividers

Output

APLL

DFS

APLL

Output

Dividers

Output

APLL

DFS

DIG12

DFS

2K8K

DFS

MCR6:DIG2SS

MCR6:DIG2F[1:0]

MCR6:DIG2AF

MCR6:DIG1SS

MCR6:DIG1F[1:0]

OUTPUT DFS

FSYNC

DFS

SYNC2K

FSCR2:INDEP

DIG2

DIG1

2K8K

ICRn:FREQ[3:0]

APLL

Output

Dividers

Output

APLL2

DFS

FSYNC,

MFSYNC

OCR4:FSEN, MFSEN

FSCR1:8KINV, 2KINV

FSCR1:8KPOL, 2KPOL

PLL Bypass

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式